Henrik Fegran

> Hi @silabs-hfegran So it seems that reset only becomes asserted at 2 ns, which is why you get warnings at that time as well. Is that being done on...

added do not merge to ensure that I do not add overconstraining assumes globally - pending those fixes this should be more or less ready to go

> hi @silabs-hfegran Would you be able to create a smaller reproducer that doesn't depend on EDA tooling, and I will take a look. Thanks for looking into this, @jeremybennett,...

@jeremybennett here is an example that only requires the compiler suite set up: make sure CV_SW_TOOLCHAIN points to your toolchain installation, check the makefile for details: https://github.com/silabs-hfegran/debug/tree/elf_issue_1391

It is resolved - there are a couple of issues I am investigating, but those should be in separate issues

@silabs-mateilga : What is the status on this? can this be closed?

While I am fully behind the reasoning for this proposition, I am a little worried about the possible implications and time that will inevitably have to be spent to get...

> Thanks for opennng this PR @silabs-hfegran. At this point, the merge conflicts don't look too bad: > > ``` > $ git merge silabs-hfegran/cv32e40s/dev > Auto-merging bin/ci_check > Auto-merging...

Merge conflicts should be OK now, runs hello world, but I will need some time to run a larger regression

> Update on the three conflicts. The first two are easy: the `cva6` directory has been deleted from CORE-V-VERIF, so `cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv` and `cva6/tb/uvmt/uvmt_cva6_tb.sv` can safely be deleted here. > >...