Henrik Fegran

I see pros and cons on both the current and proposed approach - the proposed methodology looses some flexibility if you actually do modifications in-place on cloned repositories (quick tests,...

> @silabs-hfegran Can you give a little more detail on how to reproduce, previously I would do the following > > export CV_CORE=cv32e40x pushd core-v-verif/${CV_CORE}/sim/uvmt make test TEST=clic CFG=clic_default CV_CORE=cv32e40x...

Great, thanks @eroom1966, I will update the test env. as soon as we have the register removed from the RTL as well.

> a UVM component that is configurable to accept 32-bit or 64-bit bit-vectors from either an Instruction Fetch bus (OBI or AXI) or an export. I think an instruction bus-monitor...

@Silabs-ArjanB Will close this issue when verified

Are you intending to use the old 0.92/3 or the 1.0.0 version of the bitmanip instructions? If you want to generate for the new spec, you will need to set/constrain...

> Hi @algrobman I was having the same issue. For me issue was resolved by > > 1. adding +enable_zb*_extension option in the test.yaml file present in rv32imcb target folder....