Henrik Fegran

@MikeOpenHWGroup: Are we waiting for someone/something before merging this?

Probably a Spike memory map conflict with your binary (Spike has hard coded ROMs and other simulator specific memory ranges that probably interferes), try something like the following for bare...

@MikeOpenHWGroup Is this fixed/still an issue?

This is resolved

https://github.com/silabs-hfegran/riscv-dv/commit/0b707d80452d2f7dcf68012645fc4ae6bbae2f1c (This is also present on upstream riscv-dv), there is a "legalize-warl"-functionality added to the script, that enables one to define the warl-behavior of a register with python in the...

@MikeOpenHWGroup Can we close this issue/question? There has been no activity on this discussion since june 21.

@MikeOpenHWGroup Please close this task if this is resolved - I believe that it should be though the occasional breakage may occur

 still seeing the issue here

Appears to be fixed now, thanks!

This issue can be worked around with the `-nmagic` flag to the linker.