Jiuyang Liu
Jiuyang Liu
Maybe after #4158 lands, we can find some other high performance solution w/ DPI.
how about wrapping it with “`”?
link to chipsalliance/chisel#4298
I agree `16b(e16mf2) += 4b(e4mf8) x 8b(e8mf4)` is a good point, the source of problem is vector datatype is encoded in instruction opcodes + vcsr, rather than providing tag to...
I think these functions relate to the SVA but not a part of LTL, these are not defined in LTL However we need to use it for Sequence construction to...
Thanks @fabianschuiki's suggestion! @unlsycn please try to implement the these ops in Chisel with the emulation of `RegNext` directly with Chisel, it can still live in `chisel.ltl` package, but remember...
Since the developing of logic synthesis is really a non-trivial work, I wonder rather than using CIRCT to do the synthesis job by itself, how about exporting the [aiger file](https://fmv.jku.at/aiger/index.html)...
> but instead the pass that needs to be made more generic. Agreed, #8610 also illustrated this. If some Op is not handled in `firrtl`, and delegate to `hw`, then...
> If we change the options structs to something like a CLI arguments string, would that be acceptable to you guys? I think we only need to expose these options...
Maybe `RawUnclockedVoidFunctionCall` is missing?