Jiuyang Liu comments

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                                            Jiuyang Liu

[OM] parsing depend on the ordering of Class

Is possible to delay the classOp construction?

Fix ActualDirection calculation from SpecifiedDirection

> Converted to a draft to test on large designs internally as this may have unexpected effects. T1 passes. Waiting for SiFive's designs.

Fix ActualDirection calculation from SpecifiedDirection

@jackkoenig @mwachs5 is there any plan to get this PR upstreamed?

[WIP] [tests] add test framework new design RFC

- The `verialtor` environments is designed as emulator for software engineer and the commercial custom early evaluations. It's not designed for **verification**, thus it's provided along with the docker with...

the usage of cover and cover point, and how to coordinate with backend.

cover should be migrate to the new world LTL landed in Chisel6, but we current don't have enough resource to sort it out.

(draft) Change signature of macro-based `chisel3.Bits.unary_~` to fix IntelliJ highlighting issue

Sorry for the delay response: > I think @sequencer might use a plugin for his team but generally speaking it's just been kind of lingering. However we only support fixing...

[RTL]refactor rocketv/TLB.scala: delete duplicate codes

Thanks for your contribution! Ask @qinjun-li for review

SyncReadMem ruw (ReadUnderWrite) parameter has no effect

I think we should remove or at least deprecate this and back port as bug fix to avoid misunderstanding.