Jiuyang Liu

Yes, if we really want implement this, it will entirely reinvent the base system, which is hard to accept currently, but we can take it as a feature todo which...

Basically, current flow is quite straightforward, that RTL -> Synthesis -> PaR -> DRC/LVS -> SIM -> tapeout if we consider a more real-world [demo](http://asic-soc.blogspot.com/2007/10/physical-design-flow.html): Each step should relay on...

> Your link is broken. Sorry, fixed now.

I noticed that https://github.com/ucb-bar/hammer/blob/64675e473d3de4edf77ef31d4c90045b956de3a2/src/hammer-vlsi/hammer_vlsi/hammer_vlsi_impl.py#L1297 implicitly assume that entire chip has only one voltage, I wonder If I wanna give a multi power domain design, what should I supposed to do?

Got it I’ll compose a PR latter in this week.

`tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/gds/README.txt` also shows this problem, maybe we need a post-install script for patching the bugs inside the vendor files automatically?

Additional ideas from branch `drc_lvs_refactor` by @harrisonliew, should we add libraries name and use filter to select which one we should use? This may solve this problem.

I think you should directly install Debian instead. Deepin is not a good environment from my experience.

for the rocket-chip and related repos under chipsalliance we need to maintain I think we can group them into these packages, and we may deprecate and `fpga-shells` or move to...

> Is it possible to publish Scala packages routinely with necessary dependencies, especially for the reusable parts? That would greatly simplifies other repos dependent on rocket-chip submodules. We plan to...