Jiuyang Liu
Jiuyang Liu
don't commit submodule directly, please add PR link to readme
done for u
I think we may need to remove them in Chisel and switch to the SRAM intmodule, to make it be able to work with MBIST for example...
Yes, this is intended, I'm trying fixing the publish issue recently.
It’s glad to see firrtl is eventually removing the output and input with Alignment! I wonder is this a breaking API in chisel? Or we can seamlessly migrate out current...
We may need an additional custom port for mbist/dft. This port will be ignored in the behavioral simulation. But exist in the post synthesis flow.
another thing to mention is: it's not possible to emulate the behavior for different DFT/MBIST implementation. I think it's necessary to forbid compiler to lower behavior memory with the custom...
正式版下亲测可以使用。
I have added all corner to `mmmc_corner` in asap7(ss,tt,ff), However, same problem still exist, when I look into code, I find that https://github.com/ucb-bar/hammer/blob/bc00fc2f09e3cfa0c157830698ab33b120d8883d/src/hammer-vlsi/hammer_vlsi/hammer_vlsi_impl.py#L1244 will only consume the last matched `MMMCCornerType.Setup`...
successed after adding "qrc techfile"