Jiuyang Liu

> I tried it out but got the error: > > ``` > [info] - should Decode an ADD instruction (type R) *** FAILED *** > [info] java.util.NoSuchElementException: None.get >...

Sorry for the delay again! I did some fix ups, but seems there is a bug in your decode table which was figured by Decoder.

> I expect the Instruction type in the output but currently it's a UInt. Just cast it(I know it's dirty, we should have a better name in the future) >...

Would you mind benchmark QMC vs espresso. I'm also curious to this. I thought PPA of QMC should be better, while slower than espresso. But for this case, I think...

> it'd be reasonable to consider (and I'd be willing to help develop) UVM-based or generic SystemVerilog testbenches for testing the Verilog IR. Thanks @michael-etzkorn! I think before ventilator(or any...

Just attended the Debug Spec meeting, currently it is unratified(but stable), we can start to develop a configuration now, and switch to 1.0 after ratified.

Sorry I miss deleted this comment. > It looks like RationalCrossingFull is still around, so perhaps this fix is still worthwhile? I think we can safely merge this PR.

I don’t this should be closed now. The question is > I am actually not certain this is an actual bug or an intended behavior. Can you guys check this...

See #2935, if we migrate to the "node generator" approach, the PRCI domain will live at where it was queried from.

Those modifications generally LGTM. But notice: changing `Chisel` to `chisel3` not only affects the syntax, but also the `CompilerOption`, see https://github.com/chipsalliance/chisel3/blob/2b48fd15a7711dcd44334fbbc538667a102a581a/src/main/scala/chisel3/compatibility.scala#L19 Migration from `NonStrict` to `Strict` might introduce tricky issues....