core-v-verif

core-v-verif copied to clipboard

When using [vptool](https://github.com/openhwgroup/core-v-verif/tree/master/tools/vptool) for [CVA6 Task 1434](https://github.com/openhwgroup/cva6/issues/1434), I encountered the following: 1. It does not seem possible to edit the names of previously created Sub-features. Is this deliberate? 2. Updates...

MikeOpenHWGroup

Formal: Roadmap

2

### Task Outcome Formal support needs improvements, more features, better integration, etc. ### Background information Initial formal scripts for 40s/x has been implemented for Jasper, but there is still more...

silabs-robin

Cover "debug_request asserted while dret executing while not in debug mode" scenario

2

### Task Outcome Ensure functional verification of the following scenario: - core is in debug mode. - a `dret` instruction is fetched, and begins working its way through the execution...

MikeOpenHWGroup

CV32E40X simulation errors

5

Hello! I'm having some troubles in compiling CV32E40X uvm simulation (starting from /sim/uvmt folder) that I've not encountered with CV32E40P. In particular, using the same simulation enviroment and the same...

aledolme

UVM simulation support for xsim (Vivado)

1

## UVM simulation support for xsim (Vivado) Hello everyone! When looking into the core-v projects, it seems to me that currently there is no support for a non-cost simulator that...

MikeDoingThings

Make system doesn't update the git branch/commit/tag when rerunning with a different value

3

## Improve makefile to update the git repository on incremental builds ### Task Outcome Make system that properly updates the git repository in incremental runs ### Completion Criteria in a...

christian-herber-nxp

Fetch origin/main next to specified branch/commit

3

A user can select a specific branch/commit with CV_* variables. It would be good, and not taking too many resources, to also add the origin/main branch for the reference/debugging/rebase. This...

szbieg

ISS: Missing mscratchcsw register and mnxti mismatch

13

## ISS reports missing mscratchcsw register, and mismatches upon using reserved csr-instructions to access mnxti During initialization, the `rvviRefCsrSetVolatile`-function reports an error when attempting to set `mscratchcsw` as volatile ```...

silabs-hfegran

ISACOV : wrong arguments for the toggle macro

2

Hi, I think we have another problem related to difference between get_field_imm & get_data_imm, because while looking for some missing coverage, I notice that in some instructions we're trying to...

AyoubJalali

Hello, I notice that i always get a zero for the immediate value for c.lw instruction, so i checked the isacov.log and it seems that for c.lw instruction immediate get...

AyoubJalali