ibex
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lowRISC
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
[ This is a big PR (33 files changed, 2477 insertions(+), 1886 deletions(-)), so no rush to review, and feedback very much welcome. It would be helpful to just checkout...
Build on the cosimulation environment to greatly simplify the checking needed for this test. This PR greatly simplify the test, while adding more varied stimulus by tweaking the RISCV-DV flags....
## Observed Behavior riscv_mem_error_test fails for IBEX_CONFIG={small,experimental-branch-predictor} when using the cosim flow This failure is highlighted because riscv_mem_error_test was part of the smoketest ci run against all pull requests, and...
Add support to cosim for internal interrupts (documented at https://ibex-core.readthedocs.io/en/latest/03_reference/exception_interrupts.html#internal-interrupts) > estimate 8
@hcallahan-lowrisc assigned to all of these The following debug related coverpoints are not yet being hit: - [ ] Some categories for single stepping over each instruction category - `cp_single_step_instr`...
Verify the ICache integrity and scrambling features For integrity create a testbench component to corrupt icache data and icache tags. Ensure corruptions triggered the required alert. This will require targeting...
Document and add coverage points then ensure they're getting hit for: - [ ] Data independent timing enabled whilst executing all instruction categories - Estimate 2 - [ ] Random...
Ensure CSR writes that will enable and disable the random instruction generator are emitted for some tests. This is mostly dealt with via on-going CSR work. The task here is...
Ibex has a double fault detector. A checker should be created to ensure this functions correctly and double faults should be stimulated in some tests. > estimate 4