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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Results 297 ibex issues
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It could be interesting to support RV64I as well as RV32I (imagine small helper cores, with access to the same address space as a larger 64-bit application cores). Before leaping...

Type:Enhancement
Component:RTL

The current `riscv_csr_test` uses the file https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/riscv_dv_extension/csr_description.yaml to determine what CSRs to read/write and expected values. These descriptions can change between Ibex configurations so a solution is needed to allow...

Type:Enhancement
Component:DV
Priority:P3

In #1304 , we discussed that there might be an additional cycle of latency added when entering and interrupt handler in the 2-stage configuration. See https://github.com/lowRISC/ibex/pull/1304#discussion_r594375140 for more details. We...

Type:Enhancement
Component:RTL

Document what it means to be an 'supported' configuration along with the current supported configurations and how the ibex_config.py utility works. Part of the configuration documentation can be autogenerated from...

Component:Doc
Type:Task
Component:Tool-and-Build

I see spike timeouts in DV runs of the test `riscv_pmp_full_random_test` test. Below is one example, but I see them in multiple runs (not all of them): ``` 2021-01-07T15:23:14.2445665Z Thu,...

Type:Bug
Component:DV

*This is a tracking bug. This description will be updated to reflect the current state of affairs. Comment if you have suggestions or updates.* [Yosys](http://www.clifford.at/yosys/) currently supports only a limited...

Component:RTL
Type:Task
Component:DV

I thought the FPGA Ibex offering might be enhanced by including a ready-to-use (but with the flexibility to opt-out, if desired, at synthesis time) example RISC-V debug implementation. My goal...

Hi , when IBEX_CONFIG=small, SEED=27754, ISS=OVPSIM, riscv_mmu_stress_test test failed. it is failed because there are some mismatches between rtl sim csv log and ovpsim csv log, could you please help...

Type:Bug
Component:DV

The synthesis flow uses a variety of python, shell and TCL scripts that expect certain things to be correct. When it breaks the errors it produces don't obviously point to...

Type:Task
Component:Tool-and-Build

It would be awesome if you had a "information from tape outs" type page in the documentation somewhere. I would like to see it have the following information; - [...

Component:Doc
Type:Task