ibex
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lowRISC
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Our current DV randomly produces errors on instruction fetches. The trap handler will just retry the failing the instruction when it returns so an eventual successful fetch is required for...
The tracer currently does not decode the pseudo instruction. Use it once it is supported by more tools. Actually not quite which, but it was recently mentioned in https://github.com/llvm/llvm-project/commit/249d7de1190f50178181d2477aa661cd252e294c
Tilelink has a `size` field it its message payload, that the native Ibex protocol does not have. When accessing 'standard' memory this is not a big problem. An Ibex ->...
The source files for the documentation have a mix of styles for when lines should be broken, the verification page is a notable example: https://raw.githubusercontent.com/lowRISC/ibex/master/doc/03_reference/verification.rst which contains wrapping lines at...
This PR addresses #1233 and provides some basic functionality to run riscv-compliance checks based on RISCOF. RISCOF is still in development and the switch to it in riscv-compliance is only...
This adds a beta Github action that is run on pushes and pull requests. It automatically annotates the sources with linter issues. Nothing extra is needed beyond merging. As a...
- While running ibex with riscv-compliance a package was necessary in Ubuntu. - Also as riscv-compliance repository name has been updated so it is better to update it in README...
As discussed this is just a draft to illustrate how things are shaping up. There's a few things that definitely still need doing 1. Some more documentation (e.g. a README.md...
This almost gets rid of all the hacks in the design code. Unfortunately, there's still one problem (can't pass unpacked arrays as ports) that we have to work around, but...
- Wider control of insertion frequency, all the way down every other instruction - Add dummy instructions when IF stage stalls to hide I$ timing side-channel - Add some scrambling...
