ibex
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lowRISC
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
The debug module used in conjunction with Ibex implements its functionality by having Ibex execute code that dynamically changes depending upon the commands issued to it. When the icache is...
Code coverage waivers are required for Ibex, in particular to hit our 90% coverage goal for OpenTitan V2. > estimate 2
The guys at Antmicro have been working on their Surelog+UHDM+Yosys flow and it seems that it can now build Ibex with vanilla Yosys plus their stuff as a plugin. It...
Hello, we are using IBEX with dummy instruction insertion and are doing formal verification experiments. We have observed that when a predicted branch is in the skid-buffer of the if-module...
I use the comand ```make TEST=riscv_nested_interrupt_test SEED=8037``` will have one case failed. Due to random delay for load/store, 750 cycles for timeout sometimes is not enough. when I modify dv/uvm/core_ibex/tests/core_ibex_test_lib.sv...
There is a mismatch between load/store and wdata/rdata isn't it ? https://github.com/lowRISC/ibex/blob/410ffd349da1d4c13f77b208bb3b93adb154fac0/rtl/ibex_tracer.sv#L150-L155
Hi, When I use the ```make TEST=riscv_debug_wfi_test SEED=27946``` the case 27948 will failed due to timeout. It's failed because the second instruction of main function is wfi instruction, but the...
## My Environment **EDA tool and version:** **Operating system:** **Version of the Ibex source code:**
The Ibex SS method `SimpleSystem::GetIsaString` currently returns an ISA string that contains `Xbitmanip`. We want to eventually move that to the proper bitmanip subextension names.
## My Environment I am trying to run tests on Ibex core from the binary generated from RISCV-DV verification environment. I've generated the tests separately from RV-DV and got the...
