ibex

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[dv,pmp] Timeouts because of infinite loops in the generated program

2

@marnovandermaas and I talked about this internally so I'm assigning him because of that. Please feel free to unassign yourself if you feel like it :) In the case of...

ctopal

Improve comments around check_mem_access and mmio_load/store

3

Added more comments around the function of SpikeCosim::check_mem_access() and SpikeCosim::mmio_load()/mmio_store(). Minor refactoring for clarity and flow with the comments. I guess it could be argued that this should be in...

hcallahan-lowrisc

[dv,pmp] Generating large NAPOT regions

1

At the moment RISCV-DV generates addresses randomly including when the PMP encoding is set to NAPOT. Since the NAPOT range is encoded in the address, it means that it is...

marnovandermaas

The Smepmp specification states: > Adding a rule with executable privileges that either is M-mode-only or a locked Shared-Region is not possible and such pmpcfg writes are ignored, leaving pmpcfg...

GregAC

Ibex does not reflect instruction memory changes to ICache

2

If ICache is enabled and a write to a cached instruction memory (which we are allowed to do) occurred, Ibex does not let ICache know such a store happened. As...

ctopal

[dv] Exception divergence using MML PMP mode

1

I'm seeing a divergence between Spike and Ibex when in MML mode and setting region 0 to read only. Spike throws a trap and Ibex zeroes out a destination register....

marnovandermaas

[doc] Documentation Improvement - catch all for documentation issues

5

Catch all for all issues where users have had a misunderstanding or we have some explicit knowledge that should be shared with the community via OT documentation (e.g. knowing that...

johngt

[rtl] Move to privileged spec v1.12 support

1

Ibex should move to supporting v1.12 (see ratified draft here: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf, document may have some fixes applied and new chapters integrated before the official v1.12 but only on the level...

GregAC

[dv] Add ecc error generation to memory agent

2

We need to stimulate ECC errors. The incoming bus data has integrity bits. The driver should provide incorrect versions of these at configurable random internals in a similar manner to...

GregAC

[dv] Add instructions to enable/disable data independent timing to RISC-V DV generated code

1

Our DV environment never enables data independent timing or random instruction generation. These are controlled the CPUCTRL CSR, We should emit some instructions that toggle it. Whilst strictly security related...

GregAC