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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

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It would be worth writing properties for the top-level Ibex interfaces and then trying them out on Yosys. @rswarbrick has been working on properties around the icache using Yosys so...

Type:Enhancement
Component:DV

Simply I noticed this in the Ibex. The cache is fixed always to: ``` module ibex_icache #( // Cache arrangement parameters parameter int unsigned BusWidth = 32, parameter int unsigned...

Type:Enhancement
Component:RTL

There are quite a few sections unspecified at the moment (mostly debug related). Adding them would allow linking with the `--orphan-handling=error` option to check for accidentally missed ones (that we...

Type:Enhancement
Component:Tool-and-Build

Hi, in a discussion around ROP gadgets I was pointed to a potential gadget issue with compressed instructions in upper halfwords of legal 32-bit instructions. An ROP attack could use...

Type:Enhancement
Type:Question
Component:RTL

To help users identify how their Verilator simulation of Ibex was built it would be nice to display the parameters (or name of the configuration) that were chosen when running...

Type:Enhancement
Good First Issue
Component:Tool-and-Build

## Observed Behavior Ibex handles misaligned load and store Instructions by splitting them into two separate, aligned memory accesses. This creates a data dependent execution time for these Instructions. According...

Type:Bug
Component:RTL

Hello, my team is considering using Ibex with a secure embedded operating system (SeL4) and one of the requirements we need to check off the list to support it is...

Type:Enhancement
Type:Question
Component:RTL

Hello, we are making formal verification experiments with IBEX and we for example have also found the problem from bug #1462 two days ago, with overwriting the branch mispredict address...

Type:Bug
Type:Question
Component:RTL

Is there a way to run directed tests with the ibex dv environment? I noticed that riscv-dv `run.py` allows for [directed tests](https://htmlpreview.github.io/?https://github.com/google/riscv-dv/blob/master/docs/build/singlehtml/index.html#run-directed-assembly-c-tests) to be ran with the ISS directly (runs...

Type:Enhancement
Type:Question
Component:DV

* Seed: 2031 * ibex revision: 93a76b390081b6b3b6cea2671c469f9293b998f2 * test: riscv_pmp_out_of_bounds_test (one iteration) ``` 2021-06-03T07:41:56.6319853Z riscv_pmp_out_of_bounds_test.22 2021-06-03T07:41:56.6320251Z ------------------------------- 2021-06-03T07:41:56.6320757Z Test binary: out/seed-2031/instr_gen/asm_test/riscv_pmp_out_of_bounds_test_22.o 2021-06-03T07:41:56.6321529Z sim log: out/seed-2031/rtl_sim/riscv_pmp_out_of_bounds_test.22/sim.log 2021-06-03T07:41:56.6322150Z ibex : out/seed-2031/rtl_sim/riscv_pmp_out_of_bounds_test.22/trace_core_00000000.csv 2021-06-03T07:41:56.6322723Z...

Type:Bug
Component:DV