ibex
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lowRISC
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
## My Environment **EDA tool and version:** Verilator 4.210 2021-07-07 rev v4.210 (openocd) Open On-Chip Debugger 0.11.0 (riscv32-unknown-elf-gdb) GNU gdb (crosstool-NG 1.24.0.498_5075e1f) 11.1 **Operating system:** PRETTY_NAME="Debian GNU/Linux rodete" NAME="Debian GNU/Linux"...
## My Environment fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system_cosim --RV32E=0 --RV32M=ibex_pkg::RV32MFast ERROR: In file included from ../src/lowrisc_dv_cosim_0/spike_cosim.cc:5:0: ../src/lowrisc_dv_cosim_0/spike_cosim.h:9:10: fatal error: riscv/devices.h: No such file or directory #include "riscv/devices.h" ^~~~~~~~~~~~~~~~~...
Our currently co-simulation setup checks all memory accesses, ensuring both Spike and the RTL do the same byte accesses in the same order. When a load or store generates a...
Hi guys... I am probably asking an irrelevant question so sorry: In [this makefile](https://github.com/lowRISC/ibex/blob/master/examples/sw/led/Makefile) you utilized these lines of code related to SRecord: ``` %.vmem: %.bin srec_cat $^ -binary -offset...
This commit adds memory interface and memory result interface of the RISC-V Extension Interface.
This pull request adds issue interface, commit interface, and result interface of the Core-V X-Interface for Ibex. This commit passes the verification without accelerator and with an external pseudo accelerator....
Per #1568 Main element here is to enumerate new tests that will increase coverage. New tests that are generated should be captured in this issue so that they are tracked....
## Observed Behavior When I try to simulate the Arty A7-35 example in Vivado, I get an error message in elaborate.log: ERROR: [XSIM 43-3409] Failed to compile generated C file...
Some SW use cases would prefer to have support for "direct" interrupt mode rather than "vectored" mode in the mtvec csr (support for FreeRTOS and for boot ROMs e.g. in...
## Spike log generation **Spike log file generation issue:** I am running UVM test-bench for ibex core verification. But during spike log generation, the log file generation does not end...
