Provide an easy method for adding comments to generated outputs

[mkorbel1]

Motivation

Some users of ROHD are interested in adding comments to the generated output SystemVerilog to improve readability, debuggability, and traceability for complex generation flows. While it's possible to control comments with custom module definitions, it would be nice to have a more friendly solution.

Desired solution

A simple way to add comments to generated constructs.

It would be good if this method can handle a variety of situations. For example:

• Add a comment directly above some generated SystemVerilog
• Add a comment to inline constructs using something like /* */
• Add a comment directly above other generated output (e.g. CIRCT)
• Add a comment into a construct which gets forwarded from one intermediate representation into the final output (e.g. ROHD -> CIRCT -> SystemVerilog)

Alternatives considered

• Perhaps some object that wraps other modules or constructs could be a generic way to add comments to anything. It could be like a delegating module perhaps.
• Perhaps some argument in Module's constructor could collect comment information.

Additional details

There's also the concern of general organization of output code. Adding a comment above a "block" of related logic is significantly more difficult than a comment tied to a specific module.

[mkorbel1]

The upcoming ConditionalGroup is an easy and reasonable place to add comments as well.