In `SimCompare` calculate the `signalToWidthMap` instead of manually inputting in `iverilogVector`

[mkorbel1]

Motivation

It's annoying and confusing to need to set the signalToWidth map for SimCompare after already setting port widths properly.

Desired solution

Remove the signalToWidthMap from SimCompare.iverilogVector, and instead calculate it based on the port widths of the module.

Additional details

This change might be good to do along with the CIRCT branch merge.