Zero width signals get created as 1 bit signals in generated SystemVerilog

[mkorbel1]

Describe the bug

Zero width signals get created as 1 bit signals in generated SystemVerilog

To Reproduce

Make a zero-bit port for a module and generate the SystemVerilog

Expected behavior

No signal added

Actual behavior

1 bit signal added

[mkorbel1]

This is applicable to ports for modules, so need to pay close attention to both module declarations and instantiations

Related bug for swizzling specifically: #122