DMG-CPU-Inside

DMG-CPU-Inside copied to clipboard

Quelques corrections

4

Salut Furrtek. Je suis en train de simuler la partie PPU et j'ai trouve quelques erreurs dans les colonnes l-x et a-g: -- tevo is or_3 and not nor_3 --...

rgalland

FERY inverts FF18, not DUCE

1

On page 14, the inverter `FERY` actually has it's input connected to the net `FF18`, not the inverter `DUCE`. This issue causes short circuits on the data lines each time...

msinger

On page 16, `KOTA` and `JAFA` are both AND gates, not NAND.

msinger

On page 16, `HUDA` is an AND gate, not a NAND.

msinger

On page 14, the tribuffer `GOJY` should be connected to the `!Q` output of `EMER`, not the `Q` output.

msinger

Sprite X matchers

3

Thanks for your work creating the schematics. It looks like the 6th from the left sprite X matcher WUNU and WOFO signals are reversed. WOFO is the output when count...

paulb-nl

On page 18, `ETAN` is actually a NOR, not an OR.

msinger

APU CH1 and CH2 volume envelope only work when AOI_MUX_2 cells have output inverted

2

I can't get the volume envelope function of APU channels 1&2 working without somehow inverting the clock that goes into the COUNT cells `HEVO`...`HAFO` (CH1) and `FENA`...`FENO` (CH2). They are...

msinger

On the far left hand side of page 20, the NOR gates `EMOF`...`ETOV` are labeled 000, 001, 010, ... and so on. These labels should all be bitwise complemented. Only...

msinger

On page 20, `HYNO` is actually an AND gate, not OR.

msinger