DMG-CPU-Inside
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furrtek
Reverse-engineered schematics for DMG-CPU-B
On page 9, the DTFFs of register FF25 (NR51) should have their clock inputs inverted one more time. Either by adding a little circle to the clock inputs of the...
On page 26, the full adders `EFYK` and `EJOK` should get `V6` and `V7` for their "A" inputs, not `D6` and `D7`. Btw. the the title of this page is...
The first "error" is more a confusing way of marking things- the 'D7' input to GAVU in the NR30 section of CH3_REGS is what I assume to be bit 7...
On page 25, the second input of OR gate `RUTE` should be driven by `RACU`, not `RACO`. Fixing that fixes the `MOE` output pin.
By simple I mean the output buffers that only have one connection. These are: * `SOUT` gets inverted by `KENA` on page 5. It must be inverted at the output...
`AWOD` is actually a NOR gate, not an OR gate. It generates the timing for the three chip select signals `CS`, `MCS` and `A15`.
As already pointed out in #56, the data of the OAM RAMs is inverted, so the labels `OAM_A_D0`-`OAM_A_D7` and `OAM_B_D0`-`OAM_B_D7` on pages 25, 28, 29 and 31 should have a...
Ok, #54 was just the beginning... I'm very sure all inputs of the chip are inverting. Let's go through them: * `RESET` is already correct. It represents the pad `!RST`....