DMG-CPU-Inside
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furrtek
Reverse-engineered schematics for DMG-CPU-B
There is a rare type of flip-flop that has only one output. It is used on pages 12 and 32 only. On page 12 (CH1 Sweep) there are two columns...
On page 15, `BYHO` should actually get its input from `APU_RESET`, not `BUWE`. This mistake always resets one of the two flip-flops, breaking this clock divider.
In the SVG overlay file, there is an inverter called `KYNY`. In the schematics however, this cell is called `KYLY`. (Page 12 and 13)
On page 9, all the flip-flops of registers FF24 and FF25 should be reset by `KEPY`, not `JYRO`. `JYRO` constantly keeps them under reset, making writes futile.
On page 11, the input of the inverter `BUDA` is actually connected to `AGUZ`, which outputs `!CPU_RD`.
On page 29, the fourth input of `CUGU` is actually `CAXU`, not `CAPE`. So it's "0101 5". `CUVA` should be labeled "0001 1".
On page 28, `XECY` is wrongly labeled "DFF2". It should be a "DTFF" that has a reset input. Its data input should be `D7` and its reset input should be...