DMG-CPU-Inside
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furrtek
Reverse-engineered schematics for DMG-CPU-B
On page 5, there are two occurrences of ``BURO_Q``. Those should be labelled ``FF60_D0`` instead.
If you look at page 36, the enable signal for the tri-state drivers in block "FF47 BGP" is ``!(CPU_RD2 && FF47)``, so they must be active when enable is low....
``FF00WR`` generated on page 10 by ``ATOZ`` is an active low signal. It should be called ``!FF00WR``. It is used on page 5.
In #21 I pointed out that that the net labelled ``P10_B`` is not driven by the cell ``KOLE`` like it is drawn in the schematic and that I couldn't find...
On page 21, ``VAVE`` is labelled as "BUFFER?". It is actually an inverter. This works because the tri-state drivers that are connected to ``VAVE`` have an active low enable input....
In the top right corner of page 6, ``CAGE`` is shown to have a connection to ``VYPO``. This is not true. In reality, the output of the inverter ``CAGE`` is...
In the top left of page 8 the second input of ``SOBY`` is labelled ``CPU_WR?``, but it should be labelled ``TUTU``, because it is connected to the output of ``TUTU``...
In the top right corner of page 8, the ``!OUT`` and ``OUT`` inputs of the ``PIN_BI`` cell of A3 receive the signals ``A0_A`` and ``A0_B`` respectively. It should be A3...
External pin P15 has a second signal line connected to it, just like P14. It should look like this (on page 5): 
``FF0F_RD`` and ``FF0F_WR`` generated on page 7 by ``ROLO`` and ``REFA`` are active low signals. They should be called ``!FF0F_RD`` and ``!FF0F_WR``. They are used on page 2.