Quelques corrections

[rgalland]

Salut Furrtek. Je suis en train de simuler la partie PPU et j'ai trouve quelques erreurs dans les colonnes l-x et a-g: -- tevo is or_3 and not nor_3 -- sacu is or_2 and not nor_2 -- tuvo is nor_3 and not or_3
-- ajep is nand_2 and not and_2 -- aver is nand_2 and not and_2 -- bota is nand_3 and not nor_3 -- bycu is nand_3 and not nor_3 -- care is and_3 and not or_3 -- xymu, besu, wusa, rejo, roxy, rupo, pynu, wuje and poky are NOR bistable and not or_2 -- lony and taka are NAND bistable and not and_2

En incluant tous ces changements, Je commence à voir le fonctionnement du PPU avec les 4 modes et aussi les accès mémoire sur 6 pixels au début suivi de 8 pixels. Je t'enverrai les fichiers vhdl une fois terminé, si ça t’intéresse.

[msinger]

TUBO on page 1 is also one of those bistable/latch type cells. I'm not sure what function it provides there. I find this whole circuit around that cell very confusing.

Ah, and I noticed a typo btw.: It's TAKA, not TAKE.

[msinger]

Also there are CYTO, FEMU, FYFO, GEXU and KEZU on page 13, BUTA, DALA, DANE and JEME on page 15, GOFY and GUGU on page 16, FOZU on page 18, EROX, GENA, HAZO and JERY on page 20.

Yes, I think @rgalland is right here. It makes no sense for those cells to be "power or" or "power and" cells, because many of them drive only one other cell. The "power inverter" cells on the other hand drive more cells than the normal inverters.

[msinger]

Just found ASOL on page 1 and LYXE on page 4.

[msinger]

I found out how to distinguish between those two latch types without looking at the supply rails: