DMG-CPU-Inside
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furrtek
Reverse-engineered schematics for DMG-CPU-B
On page 1 ``CLKIN_A`` is fed into ``UFOL`` which drives the ``!RESET_DIV`` signal. If ``CLKIN_A`` were a clock, then it would constantly reset the DIV register. I simulated the first...
The gates `APYS` on page 5 and `EFOP` on page 9 each have the label `FROM_CPU` at one of their inputs. This label is wrong. It should be `T1T2` with...
On page 7, the label `CPU_WR_RAW` on input 4 of NAND gate `REFA` is wrong. It should be `CPU_WR`.
On page 1, the clock input of `AFER` should be driven by `BOGA`, not `BOMA`. `BOMA` drives the inverse clock input though. So in the schematic `BOGA` should either be...
On page 18, the first input of the AND gate `GEDO` is wrongly connected to `BUFY_256Hz`. It should be connected to the `Q` output of the DTFF `FEXU`. I noticed...
On page 18, the output of the inverter `ATOK` just ends in an arrow without a label. It is connected to the wave RAM. I believe it could be the...
On page 18, the inverter `FALU` should be connected to the `!Q`output of the counter cell `GAPO`, not the `COUT` output.
Sortie de TAME reliée à l’entrée 2 de TOMA uniquement. Et donc, TOXE Q relié à TYFO D, TAME E2, TYTU E1 et TYNO E1.
On page 16 and 18 the nets labeled `KUTU`, `KUPE`, `KUNU`, `KEMU`, `KYGU`, `KEPA`, `KAFO`, `KENO`, `KEJU`, `KEZA` and `JAPU` are actually driven by the `!Q`outputs of their respective counter...