calyx
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calyxir
Intermediate Language (IL) for Hardware Accelerator Generators
Fixes some lingering issues AXI generation. Namely, `AxBURST` ports and internal signals are now generated and assigned to a default of `0b10` in order to used the default INCR type...
Fixes https://github.com/cucapra/calyx/issues/165. We should make at least one frontend use these memories. Eventually, this will make it easier for us to use UltraRAM memories on FPGAs instead of BRAMs. We...
Main tasks - [ ] Start generating more kernels through TVM Need to decide a) which other kernels to use besides lenet (probably VGG 16 and SqueezeNet but we need...
The `MergeStaticPar` and `StaticParConv` only act upon groups and cannot be run on `invoke` statements. Since `group2invoke` turns a lot of simple groups into `invoke` statements, these passes are less...
In the fud folder, if you haven't manually created a .config folder, then there it says there is no .config/fud file that exists and throws an error. In order to...
When I run a simple example with negative numbers through a 2d-matrix multiplier, I get two different outputs depending on if I use verilator or the interpreter (although the result...
Currently, `infer-share` does not detect `foo` as shareable. ``` component foo() -> () { cells { lt = std_lt(32); r = std_reg(32); w = std_reg(32); } wires { comb group...
Once we have #1123 merged, we'll have support for fine-grained concurrency in Calyx. We should write up a document explaining what it is, what the guarantees and restrictions are, and...
Currently, we have two ways of running Calyx-generated RTL: * Simple hardware, open-source simulator: This is the "normal" way of running Calyx programs. We compile the core design to Verilog...
Lenet is the biggest kernel that we use for evaluating Calyx. Since we've fixed the relay frontend CI, we should also add Lenet to the integration test suite to catch...