calyx
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calyxir
Intermediate Language (IL) for Hardware Accelerator Generators
We often use the `-s .` syntax for `fud` to pass a value for `` to ``. However, it's easy to get the names of the flags wrong which fud...
Our CI now uses the docker image. We should make it the recommended way to work with Calyx. Couple of complexities I ran into when setting up CI that we...
Over the process of trying to convert Onnx models to Calyx code, I've run into a few issues. Some of them are rather minor and I've tried to just work...
Currently, we have a tool in tools/data_gen which can generate a json file of memories from a .futil file. #1003 gives the tool the power to generate just unsigned, 32-bit...
Companion PR to https://github.com/cucapra/dahlia/pull/395
We have already seen that manually separating Calyx files with a seq of (for example) 20 invokes, into 20 separate Calyx files with one invoke each, can dramatically speed up...
Just writing up a small idea that emerged during this week's meeting. It would be nice to have a primitive use/statistics pass at the Calyx level to determine total counts...
Currently, the backend is in-charge of collecting all assignments to a port and generating an equivalent state in Verilog. For example: ``` a.in = g1 ? b; a.in = g2...
Another shot to answer the evergreen undefinedness of undriven signals in Calyx (https://github.com/cucapra/calyx/discussions/922). In its most reduced operational form, it asks when is it safe to provide `'x` as the...
When running resource estimation, the `main_drc_routed.rpt` file provides the following warning: > DPOP-3#1 Warning PREG Output pipelining DSP mult_pipe0/comp/out_tmp0__0 output mult_pipe0/comp/out_tmp0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will...