calyx
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calyxir
Intermediate Language (IL) for Hardware Accelerator Generators
With #1145, Calyx has rudimentary support for memories with sequential read and writes. While the specific implementation of the memory in that PR is a 1-cycle read, 1-cycle write memory,...
This PR adds memory-type (`Sequential` or `Combinational`) data, explicit dimensionality sizes and `idx` sizes, and makes `yxi` look for both `@external` memories and `ref` memories (before it was limited to...
Implement a wrapper in Calyx for [Berkeley HardFloat ](http://www.jhauser.us/arithmetic/HardFloat-1/doc/HardFloat-Verilog.html) `fNToRecFN` (IEEE standard format to HardFloat recoded format) Verilog module (adopted based on [PyMTL's corresponding file](https://github.com/pymtl/pymtl3-hardfloat/blob/master/HardFloat/source/fNToRecFN.v)). And include a corresponding test...
Add the BTOR2 interpreter along with infrastructure necessary for integrating the interpreter with Calyx. I also created a dummy BTOR2Add primitive that reads a hardcoded program from disk and tested...
Currently Cider 2.0 cannot print out the contents of memory in a way that is compatible with the json tooling we use for snapshot testing. The old infrastructure for this...
We're finally at point where we can start running programs through Cider 2 and thus it now makes sense to have a tracker for the ongoing efforts to reach parity...
Kinda seems like fud2 should become a [hypergraph][]. It's currently a graph: vertices are states, and edges are operations (transformations between states). But the need for ops with two inputs...
Branching off of #1603 - one blocker for deprecating `@external` and adopting `ref`'s synthesis mode everywhere is that currently the version of Verilog generated by synthesis mode (externalizing all memories)...
The following program, when run through fud with `fud e --from calyx --to vcd --through verilog` creates a circular combinational logic error (Simulating with `icarus-verilog` just hangs): ``` =====STDERR===== %Warning-UNOPTFLAT:...
# First step / end goals of performance dashboard? # ## What benchmarks would we use? (needed to test metrics we produce on the dashboard): ## - systolic arrays -...
