calyx
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calyxir
Intermediate Language (IL) for Hardware Accelerator Generators
A pass that marks ports as stable or unstable depending on where they receive values from. If the value comes from a continuous assignment rooted in stateful elements, the read...
In general, hardcoded top-level function/filenames are in general expected to be called `main` in various `.tcl` scripts. However, for the Vivado HLS flow, top-level functions and files are named `kernel`....
The [unrolled MVT](https://github.com/cucapra/calyx-evaluation/blob/master/benchmarks/unrolled/linear-algebra-mvt.skip) benchmarks generates invalid verilog: ``` %Warning-UNOPTFLAT: /var/folders/sk/f158_qn147vc0jhjsfdcswq40000gn/T/tmpweji9c61:1076:18: Signal unoptimizable: Feedback to clock or circular logic: 'main.add9_right' 1076 | logic [31:0] add9_right; | ^~~~~~~~~~ ... Use "/* verilator...
Sometimes we only want to access a certain subset of the bits in a multi-bit bus. `std_slice` provides limited functionality in this regard. For example, in SV, we could access...
With ` runt -i frontends/mrxl/test -d` ``` mrxl correctness (3 tests) ✓ pass - frontends/mrxl/test/add.mrxl ? miss - frontends/mrxl/test/dot.mrxl ~ 1│+ ---STDERR--- 2│+ ERROR: Stage 'futil' had a non-zero exit...
Currently, when a signal in a Calyx program doesn't have a meaningful value during interpretation, we currently just say that it has the value zero. For example, when a group...
This is from a discussion with @vegaluisjose At the moment, our lowering pass completely removes control, but leaves a lot of guards in the `wires` section. We can go further...
Update by @rachitnigam: The memory primitives in Calyx's standard library allow for combinational reads. Different FPGAs and ASIC processes might allow for different kinds of memories, some of which might...
We now have each function of the VGG Net implemented in Dahlia, at least to simulate a single example all the way through. While there exist a single test or...
Several cells in the library have input and output bitwidths. A bitwidth reduction pass analyzes the uses of output ports and, based on the use, changes the input bitwidths. For...