calyx
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Intermediate Language (IL) for Hardware Accelerator Generators
@rachitnigam brought this up on the CIRCT PR and issue about compiling Calyx to CIRCT's core dialects: https://github.com/llvm/circt/issues/2892#issuecomment-1128162272. Quoting that comment: > A reasonable next goal is to lower all...
## FuTIL optimizations - [x] Redundancy elimination (#141) - [x] Static Timing (#154) - [x] Resource Sharing - [x] Pipelining (#200) - [x] Bitwidth analysis (#198) - [ ] Control...
To reproduce, run: ``` fud exec -s verilog.data tests/correctness/tcam/lpm.futil.data tests/correctness/tcam/lpm.futil --to dat -v -s futil.flags '-d static-timing' ``` The reason we haven't caught this before is because this doesn't occur...
The current implementation of `par` interpretation algorithm always runs the parallel blocks in serial order. We've discussed a simple extension where the order in which the children are run is...
**Goals** 1. Prove equivalence or in-equivalence of calyx programs by comparing outputs with same data as input. 2. Find bugs in calyx compiler (input fuzzing) 3. Find bugs in the...
This has come up most immediately in the interpreter having trouble with programs lowered via the WireInliner. The short version is that there can be transient assignment conflicts prior to...
Opening the issue for @cgyurgyik as promised in the Friday meeting. Details of the source location metadata format are found in (#971 with minor tweaks in #973). I can link...
I think it would be a good idea to add a few tests (one specifically for `sqrt`) for the icarus-verilog backend. Perhaps benchmarks as well? This would require some additions...
When a breakpoint or watchpoint is set on a group which is called multiple times in succession it accidentally treats it as happening only once but taking X times longer...
We’ve been talking about so-called “method-based interfaces” for calyx for a while. The idea is to support components that can be called in multiple ways. For example, we can call...