calyx
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calyxir
Intermediate Language (IL) for Hardware Accelerator Generators
We call it `out_remainder`, but instead return the output of the modulo.
I was debugging #329 and wrote down a simple script for differential testing. Then, I slowly reduced the program to find a minimal program. A few problems that need to...
With the dependency on the python frontend library for the systolic and ntt frontends and the requirements for `fud`, we have too many commands we need to run to get...
Control signals in Calyx programs often have high fan outs. For example, in a `par` statement with `n` children, the `go` signal to the corresponding group to implement the control...
A 32 bit adder can perform 16-bit adds. A 16-bit register can shore 8-bits of information. Share ‘em. obviously needs some attribute-based knowledge of the primitives.
There are three possible optimizations that can benefit code generated from Dahlia: 1. Constant folding ``` let x = 5; // X is never written to x + x; 10...
Currently, the systolic array generator naively generates a `seq` of `par` to enable the compute and data movement groups. However, this means that for the same systolic array, as the...
Thought it would be useful to open a draft PR to allow time to get feedback while classes are starting and I'm less available. This is nearly done. Pull request...
Add a pass that eliminates unused ports of a component. In doing this, we also get rid of any assignments to those ports and allow the various dead-cell elimination passes...
When I try to compile the following program (generated by circt and amc): ``` import "primitives/core.futil"; import "primitives/binary_operators.futil"; extern "amc.v" { primitive mem_0_prim[WIDTH, PORT0_SIZE, PORT0_IDX_SIZE, PORT1_SIZE, PORT1_IDX_SIZE](@clk clk: 1, port0_addr0:...
