calyx
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calyxir
Intermediate Language (IL) for Hardware Accelerator Generators
An unintuitive problem that @paili0628 ran into for the #959 pass implementation is that the default pipeline now needs to call `dead-group-removal` twice. However, the `-d ` option disables *all*...
This is a tracking issue to audit the types of data being used by the frontends to inform the future development of custom data formatting in the interpreter and debugger....
The current printing is somewhat hard to make sense of, some improvements would be: - [ ] Add some colour to the output to distinguish the types of things going...
The `top-down-st` pass attempts to generate one big, top-level static FSM for programs. However, currently, it has some outright bugs in the presence of conditionals and parallel threads. ## Conditional...
It might be useful to add more logging capabilities to the interpreter since we've added slog. This could make future internal debugging a bit easier and could potentially offer more...
Currently, `ir::Port` can either be a port on a cell or a group's hole. This was a decision I made when reimplementing the IR and was mostly based on the...
This came up over here: https://github.com/cucapra/calyx/pull/909#discussion_r811391088. The multiplier and some of the other non-trivial primitives use multiple stages internally, and it should be possible to pipeline them with II=1. Now...
I've pondering this for a while. If I understand correctly, multi-dimensional memories are not directly mappable when doing synthesis, which probably means that at some point, the underlying synthesis toolchain...
## Problem When I wanted to loop only 4 times using 2-bit number representation for loop counts and 2-bit `le` operator, I ran into a problem where after checking that...
Just going to write this out to get it out of my head. #828 added support for re-ordering assignments into a dataflow order. This could enable a (possibly) faster algorithm...