Implement memories with sequential reads

[rachitnigam]

Fixes https://github.com/cucapra/calyx/issues/165. We should make at least one frontend use these memories. Eventually, this will make it easier for us to use UltraRAM memories on FPGAs instead of BRAMs.

We can design a parameterized memory which takes read and write latencies as parameters. However, we don't currently have a way to specify the @static behavior of such memories because they are parameteric