amaranth

amaranth copied to clipboard

Hi, some of my code recently started failing with this exception after a Python version bump: ``` Traceback (most recent call last): [...] File "/usr/lib/python3.10/site-packages/amaranth/hdl/xfrm.py", line 209, in on_statement new_stmt...

Mrmaxmeier

[amaranth-boards] Jinja2 dependency seems to require pinning of MarkupSafe dependency

1

After having looked [the raw logs of CI](https://pipelines.actions.githubusercontent.com/serviceHosts/514a3656-e17d-4829-9e26-0d12794b3619/_apis/pipelines/1/runs/259/signedlogcontent/2?urlExpires=2022-09-19T03%3A32%3A26.4017497Z&urlSigningMethod=HMACV1&urlSignature=jSEyzozlaeoTeSSI26fy2JFvw89st9D4ifa1iiTihBM%3D) for [my PR to amaranth-boards](https://github.com/amaranth-lang/amaranth-boards/pull/204), it seems that the jinja2 version used in amaranth relies on an old Markupsafe version (2.0.1), the...

sporniket

Fixes #713 by requiring MarkupSafe anterior to 2.1.0

3

sporniket

Fixes #713 by always using latest version of Jinja2

4

(another experiment to see what break)

sporniket

Translate ArrayProxy to pattern matching when supported

4

Current the value compiler translates ArrayProxy into if-elif trees which can cause the compiler to crash due to deep recursion (#359). This patch instead translates them into pattern matching when...

Jimx-

Make AST nodes immutable

2

Right now it's actually possible to do things like "set `sig.width` on a `Signal`" or "modify `c.parts` on a `Cat`". This has never been explicitly advertised as something that is...

whitequark

Normalize diagnostics to use either a backtick or a single quote, not both at random

2

Bikeshed: which of these should we use?

whitequark

Use nextpnr-himbaechel on Gowin

13

I need help with what appears to be a bug somewhere in the Amaranth/Yosys/Apicula ecosystem. It could also be me because this is my very first day playing around with...

mobilinkd

Conditional assignment to a slice can generate invalid Verilog

2

The following code ```python from amaranth import * import amaranth.back.verilog m = Module() output = Signal(2) enable = Signal() with m.If(enable): m.d.comb += output[0].eq(1) with open('test.v', 'w') as f: f.write(amaranth.back.verilog.convert(...

daniestevez

Fragment flattening can cause local domains to get merged

2

``` from amaranth import * from amaranth.back.verilog import convert a = Signal() d = Signal() q1 = Signal() q2 = Signal() clk1 = Signal() clk2 = Signal() m1 = Module()...

mwkmwkmwk