amaranth

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- RFC PR: https://github.com/amaranth-lang/rfcs/pull/43 - Implementation and deprecation PR: https://github.com/amaranth-lang/amaranth/pull/1140 - Removal of deprecated feature PR: N/A (for milestone 0.7)

whitequark

back.rtlil: Opportunistically trim zero and sign extension on operands.

3

Fixes #1148.

wanda-phi

Driver-Driver conflict causes unclear error message [regression from 0.4]

3

The following code warns that the hierarchy will be flattened: `DriverConflict: Signal '(sig signal)' is driven from multiple fragments: top, top.test; hierarchy will be flattened` proceeds with Yosys, yielding a...

ECP5-PCIe

[WIP] Add Display statement.

2

Intent: fixes #432. * Rebase of dc6a805, which adds the `Display` statement with support in simulation. * Minimally working RTLIL backend support. * Confirmed this works in CXXRTL. TODO: *...

charlottia

New IR causes DSP inference issues with Quartus

1

The following design (within the Details) infers 2 DSP blocks: `Info (21062): Implemented 2 DSP elements`. ```python from amaranth import * from amaranth.lib import wiring from amaranth.lib.wiring import In, Out...

tpwrules

- RFC PR: https://github.com/amaranth-lang/rfcs/pull/45 - Implementation PR: https://github.com/amaranth-lang/amaranth/pull/1142 - Documentation PR: https://github.com/amaranth-lang/amaranth/pull/1228 - Removal PR: N/A (milestone 0.6)

whitequark

Inferring True Dual-Port BRAMs with the new IR on Series 7 and ECP5

2

I'm trying to infer a true dual port BRAM on a Xilinx Series 7 chip, but I'm not having much luck. I've written the following to try to map the...

fischermoseley

[WIP/PoC] Add async testbench functions

1

zyp

Implement RFC 30: Component metadata.

7

jfng

infinite loop in NIR builder on a trivial comb loop

1

The following results in an infinite loop: ``` from amaranth import * import amaranth.back.rtlil m = Module() a = Signal() m.d.comb += a.eq(a) amaranth.back.rtlil.convert(m, ports=[]) ```

wanda-phi