amaranth
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A modern hardware definition language and toolchain based on Python
It would be great to have a linter which reports on things like "you are assigning signals of different widths", "you assign this comb signal in one branch of this...
# Aggregate data structure library RFC ## Summary Add a rich set of standard library classes for accessing hierarchical aggregate data an idiomatic way, to fill one of the two...
While creating a large gate level multiplier in amaranth I noticed that it took a long time to write out the Verilog. A simple test case: ``` #!/usr/bin/python3 import sys...
Yosys + nextpnr-xilinx + prjXray may be used as toolchain to build bitstream for artix and zynq devices. This PR add support for this combo and introduce since Symbiflow and...
# Discriminated Unions / Enums This (sub)RFC builds on #697. As proposed in #697, first-class discriminated unions could be very useful. ## Motivation While discriminated/tagged unions can be built on...
```python from amaranth import * from amaranth.cli import main class UARTReceiver(Elaboratable): def __init__(self, divisor): self.divisor = divisor self.i = Signal() self.data = Signal(8) self.rdy = Signal() self.ack = Signal() self.err...
Fixes https://github.com/amaranth-lang/amaranth/issues/706
This PR adds initial support for running the [OpenLANE](https://github.com/The-OpenROAD-Project/OpenLane) ASIC flow with the sky130A PDK. This PR is initially a draft as there are still some things to be worked...
_Originally posted by @whitequark in https://github.com/amaranth-lang/amaranth/issues/703#issuecomment-1104789392_ > In general, if the simulator doesn't converge, it means an issue with the input netlist. I'd say that the appropriate way to handle...