Complex Class verilog error

[stevobailey]

Running the following chisel code produces a Verilog syntax error. At a high level, this code just takes the output of some submodule (BiplexFFT) and computes the power.

import Chisel._

class Splash2IO extends Bundle {
  val data_in = Complex(SInt(width=16), SInt(width=16)).asInput
  val data_out = SInt(OUTPUT, 64)
}

class Splash2 extends Module {
  val io = new Splash2IO

  val biplex = Module(new BiplexFFT)
  biplex.io.data_in := io.data_in
  io.data_out := (biplex.io.data_out.real * biplex.io.data_out.real) + (biplex.io.data_out.imag * biplex.io.data_out.imag)
}

class BiplexFFTIO extends Bundle {
  val data_in = Complex(SInt(width=16), SInt(width=16)).asInput
  val data_out = Complex(SInt(width=64), SInt(width=64)).asOutput
}

class BiplexFFT extends Module {
  val io = new BiplexFFTIO
  io.data_out := io.data_in
}

object Work {
  def main(args: Array[String]): Unit = {
    val first_chisel_arg = ((args.zipWithIndex.filter(_._1 contains "--").map(_._2)) :+ args.length).reduce(math.min(_,_))
    val build_args = args.slice(first_chisel_arg, args.length)
    require(args.length>0, "Need some arguments")

    args(0) match {
      case "-build" =>
        chiselMain(build_args, () => Module(new Splash2));
    }
  }
}

Here is the generated Verilog.

module BiplexFFT(
   ...
endmodule

module Splash2(
    input [15:0] io_data_in_real,
    input [15:0] io_data_in_imag,
    output[63:0] io_data_out
);

  wire[63:0] T3;
  wire[127:0] T0;
  wire[127:0] T1;
  wire[127:0] T2;
  wire[63:0] biplex_io_data_out_real;
  wire[63:0] biplex_io_data_out_imag;


  assign io_data_out = T3;
  assign T3 = T0[6'h3f:1'h0];
  assign T0 = T2 + T1;
  assign T1 = $signed(biplex_io_data_out_imag) * $signed(io_data_out_imag);
  assign T2 = $signed(biplex_io_data_out_real) * $signed(io_data_out_real);
  BiplexFFT biplex(
       .io_data_in_real( io_data_in_real ),
       .io_data_in_imag( io_data_in_imag ),
       .io_data_out_real( biplex_io_data_out_real ),
       .io_data_out_imag( biplex_io_data_out_imag )
  );
endmodule

The following lines:

  assign T1 = $signed(biplex_io_data_out_imag) * $signed(io_data_out_imag);
  assign T2 = $signed(biplex_io_data_out_real) * $signed(io_data_out_real);

Should be:

  assign T1 = $signed(biplex_io_data_out_imag) * $signed(biplex_io_data_out_imag);
  assign T2 = $signed(biplex_io_data_out_real) * $signed(biplex_io_data_out_real);