Verilog backend not work when wiring bundle from a class to another IO pin

[kevinlinger]

I have a scala class ModInt that looks like:

class ModInt extends Bundle { val dat = new BigUInt() val mod = new BigUInt()

def +...

}

and BigUInt looks like: class BigUInt() extends Bundle { val data = UInt(INPUT, 256) val oflo = Bool(INPUT)

def... }

when I instantiate a ModInt object, myModInt, and then try to wire myModInt.dat.data to an IO pin of a chisel module:

val modularMultiply = Module(new modMultiply()) val myModInt = new ModInt ... modularMultiply.io.operandA := myModInt.dat.data

the Verilog backend breaks (The C backend works perfectly fine), I get the following error:

// COMPILING class Work.pointAdder(2) started inference finished inference (11) start width checking finished width checking started flattenning finished flattening (630) resolving nodes to the components error java.lang.NullPointerException java.lang.NullPointerException at Chisel.Backend.collectNodesIntoComp(Backend.scala:311) at Chisel.Backend.elaborate(Backend.scala:525) at Chisel.VerilogBackend.elaborate(Verilog.scala:767) at Chisel.chiselMain$.apply(hcl.scala:203) at Work.Work$.main(work.scala:8) at Work.Work.main(work.scala) at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source) at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source) at java.lang.reflect.Method.invoke(Unknown Source)

[sdtwigg]

Instantiating directioned nodes inside of a module but not in an I/O is dangerous. Try not defining those Bundles as I/Os (and then just using asInput and asOutput in your I/Os) or constructing those internal nodes with .asDirectionless (although this seems more hacky).

[da-steve101]

this issue seems solved. Following code working

  @Test def issue99() {

    class BigUInt extends Bundle {
      val data = UInt(INPUT, 256)
      val oflo = Bool(INPUT)
      override def cloneType() : this.type = new BigUInt().asInstanceOf[this.type]
    }

    class ModInt extends Bundle {
      val dat = new BigUInt()
      val mod = new BigUInt()
      val datOut = (new BigUInt).flip()
      val modOut = (new BigUInt).flip()
      override def cloneType() : this.type = new ModInt().asInstanceOf[this.type]
    }

    class UserMod extends Module {
      val io = new ModInt
      io.datOut := RegNext(io.dat)
      io.modOut := RegNext(io.mod)
    }

    chiselMain(Array[String]("--v",
      "--targetDir", dir.getPath.toString()),
      () => Module(new UserMod()))
  }