Catting a UInt of width 0 leads to strange sim results

[da-steve101]

The catting a UInt of width 0 onto a value causes strange results in c simulation

class UserMod extends Module {
  val io = new Bundle {
    val in = UInt( INPUT, 8 )
    val out = UInt( OUTPUT, 8 )
  }
  io.out := ( io.in ## UInt( width = 0 ) )
}

class UserModTests( c : UserMod ) extends Tester( c ) {
  poke( c.io.in, 3 )
  step(1)
  expect( c.io.out, 3 )
  poke( c.io.in, 5 )
  step(1)
  expect( c.io.out, 5 )
}

The output is

  POKE _read__iw__iw__iw__iw_UserMod.io_in <- 0x3
STEP 1 -> 1
  EXPECT _read__iw__iw__iw__iw_UserMod.io_out -> 0xe0 == 0x3 FAIL
  POKE _read__iw__iw__iw__iw_UserMod.io_in <- 0x5
STEP 1 -> 2
  EXPECT _read__iw__iw__iw__iw_UserMod.io_out -> 0xe0 == 0x5 FAIL

[ucbjrl]

This requires explicitly enabling zero-width wire support. Try adding the

--W0W

parameter to the chiselMain() argument list.

We should either make this (zero-width wire support) the default, or generate an error when we encounter zero-width wires.