SpinalHDL

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Recompilation of LimitedCounterIncFormal would cause an infinite compiling.

3

When I recompile by ``` shell sbt "tester/runMain spinal.tester.code.LimitedCounterIncFormal" ``` without clean on Windows. The sbt would stuck into infinite loop of displaying "[info] Compiling 2 Scala sources to xxxxxx\SpinalHDL\tester\target\scala-2.11\classes...

Readon

Comment rtl entity

8

Comments can be added to the rtl entity

Snoopy87

[WIP]Yosys integration

48

### Introduction This PR will introduce a way to interface/integrate with yosys without leaving scala. This PR contains (in detail) * A way to abstract any CLI-commands and keep written...

wifasoi

Cannot resolve symbol libraryDependencies

2

I want to use Intellij to configure, and I see this problem in the build. SBT file, what should I do？ `import sbt.Keys.libraryDependencies ThisBuild / version := "0.1.0-SNAPSHOT" ThisBuild /...

0806gcx

Memory: multiple ports with writeFirst should be permited.

6

This allows logic to be generated that will allow address collisions to be resolved between a write & read port (eg to reduce latency of a FIFO).

nbstrike

How to set the name of Stream.queue() ?

7

Hi, when I use Stream.queue() to generate stream fifo. `val streamInQueue = io.flowIn.toStream.throwWhen(!io.enable).queue(256)` The generated fifo and signal name is streamFifo_1. Is there any method to use the name of...

dahuwei

When does spinal.sim support vcs or modelsim

1

I am FPGA developer，I often use some ip core，so，When does spinal.sim support vcs or modelsim

qgzln

Simulation issue When a blackbox without reset

2

When I try to simulate a blackbox ram without. It occurs `java.util.NoSuchElementException: key not found: (reset : Bool)` Just the document's BlackBox example with `SimConfig.withVCS.compile....`

C1oud555

How to update spinal to the latest version for existing projects

4

I am a beginner, I would like to ask how to update spinal to the latest version for existing projects.

Aaronwangyilun

how to check a signal is unload?

4

Hi, is there a method to check a signal is unload? I thought `dlcIsEmpty` can be check unload, but I‘m Wrong... ```scala val aa = B"3'd0" val bb = aa...

dxsm