SpinalHDL
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SpinalHDL
Scala based HDL
I created the following code that takes a vector of inputs and counts the number of elements that surpass a threshold (100). The resulting verilog code uses non-blocking assigns --...
 As show in the picture，I reassign myBits_8bit，but generate rtl reassign to myBits_32. Is it a bug?
Kind of a sub-thread of #137 specific to resets. At the moment, all statements are generated implicitly inside a block that only runs when the system is running. This kind...
The generated Verilog code contains a header like this: ```Verilog // Generator : SpinalHDL v1.3.9 git head : 0f14fcc31e1099ab7fb106009a605d0d6e7be21a // Date : 12/03/2020, 23:01:57 // Component : SlowdownTest ``` Including...
The RoundDown and RoundToZero in SInt, and RoundDown in UInt, the "align" parameter of which is not defined a default value.
```scala class MyBundle extends Bundle{ val a,b = UInt(8 bits) // or : val a = UInt(8 bits) // val b = UInt(8 bits) } object Play2 extends App{ import...
```scala class MyTopLevel extends Component { val we = Bool() val addr = UInt(10 bits) val mem = Mem(UInt(32 bits),1024) mem.generateAsBlackBox() we := True addr := 10 val readData =...
due to some reasons ,sometimes I want to create my own bus(not using Stream or Valid) like: ```scala class MyBus extends Bundle with IMasterSlave { val ready = Bool() val...
@Dolu1990 Hello, I try to add reports to my code,like this: ```scala when(nestUpdate.fire){ assert(nestUpdate.set === status.set && nestUpdate.tag === status.tag && nestUpdate.clientID === io.MSHRID) dirData.state := nestUpdate.newState report(s"dir state in...