SpinalHDL
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SpinalHDL
Scala based HDL
Is still not perfect, bet you can check the result here: https://travis-ci.com/wifasoi/SpinalHDL/jobs/195742247 There are still some u-test that do not behave, so I'll mark this PR as a WIP. Explanation:...
I want to define a default value for a signal without totally disabling the check for assignment overlaps. Using `.allowOverride` the check will be disabled totally for the signal. So...
I am designing a small module that contains a register bank, but it seems like the RO type register has a problem. In the RO method _(spinalhdl-lib_2.12-1.6.1-sources.jar\spinal\lib\bus\regif\RegInst.scala line 139)_ line...
In the Spinal lib，I find there is axi4 crossbar,axi4 decode ,Will there be axilite4 crossbar and axilite4decode in lib in the future?
In `SpinalHDL/core/src/main/scala/spinal/core/Bool.scala`, line 137: ``` def fall(): Bool = ! this && RegNext(this) ``` The register is never initialized in the code. Sometimes it will be mistakenly initialized to True...
@Dolu1990 , The current MEM blackbox looks like several fixed interface forms(`Ram_1w_1ra` ,`Ram_1w_1rs`,`Ram_1wrs`,`Ram_2wrs`). It may not be suitable for ASIC design Because of different teams or companies, MEM wrapper has...
Consider providing stand-alone, all-batteries-included, no-network-required installer or container
I've been in the use-languages-to-generate-netlists game for a long time, starting with my involvement in developing BYU's JHDL more than 20 years ago, and continuing with lots of similar tools...
For Instance ```scala class top extends Component{ val a,b = UInt(8 bits) var c = a + b + 1 val d = a.asSInt + b.asSInt val e = a.resize(11)...
While playing around with `Mem`, I came across some questionable behavior that I'd like to discuss: 1. A synthesized `write` port with `enable` signal will continue to write during resets....
