SpinalHDL
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SpinalHDL
Scala based HDL
Currently, SpinalEnum does not support print in simulation, that: ``` println(${some SpinalEnum val} ``` will print it as `null`.
There are cases where there are two separately monitored streams whose payloads are functionally coupled and must be checked during simulation, such as the address and data of some buses...
It is not the first time it happens to me, but last time I was unsure about my sanity. Basically, when I have a debugging issue and set `withWave` or...
 As above, is there a method as ```scala autoConnect(A,B,C,D, io, function() { A.sig1 B.sig1_aa }) ``` make module A/B/C/D and top.io autoConnect with same port name instead of use...
This patch adds support for multiple CS pin, useful if anyone wants 128MB or 256MB with SDRAM. It's tested on a board with 4 IS42S16320F SDRAM chips, forming 32bit x...
Half a year ago we discussed merging RegIf and BusSlaveFactory into a single thing. This is the current state of my work. Currently, there are implementations for Axi4Lite and APB3....
The code looks cleaner this way and it’s obviously easier to keep line endings properly in sync. Can be merged instead of #327 if the style is considered beneficial.
I decoupled the doc generation from the BusIf structure to make it easier for users to implement their own generators. They can now simply implement a BusIfVisitor. I also ported...
Snoopy
- Rework AhbInterconnect (Decode + arbitrer) - Add AHB tests for arbitrer/decoder/interconnect - Add PhaseInitReg (Init all register uninitiated ) - You can add comments of a component in the...
This is a *hopeful* solution to https://github.com/SpinalHDL/SpinalHDL/issues/251 that I raised. ComponentEmitterVerilog.scala ----------------------------- - Added a check where if an output of a subcomponent was connect to an output of the...
