SpinalHDL
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SpinalHDL
Scala based HDL
when i try to use **mixed-width function** in **RAM/ROM**,error occurs and i have no idea about it.if it possible to give a demo code to demonstrate how to use **mem.writeMixedWidth**...
@Dolu1990 Hello,I'm using spinal to write a multi-core cache. But when I try to simulate my code,I found that I can't use things like Bundle in my testbench,and that is...
I'm trying to define new stream based on Stream(Fragment(T)), it works well when I use master Stream Fragment(MyStreamData(32)) for io.output, but it doesn't work when I use MyStream object to...
There is no way to set radix for the switch statement, but sometimes binary representation may make more sense than octal. So it would be nice to be able to...
Question1： Why is the state of FSM and Emun defined with define? This introduces hidden risks, for example: There are 3 verilog files, a.v, b.v and c.v. The synthesizer reads...
As already discussed on Gitter, here is an example component that does a couple of translations to a Vector of Streams. Ideally I would like all signals stages1-stages5 to be...
Hi, thanks for great work. Are there any plans to implement AXI4-Stream? I think it would be a really nice to have addition to family of buses and looking at...
When using Verilator, we usually need to pass Verilator configuration files to Verilator like normal Verilog file. The Verilator manual suggests that: > Note that file or line-specific configuration only...
Sometimes it is convenient to have an initial value in FPGAs (registers initialized during bitstream load) while, at the same time, allowing a user-triggered reset pin to go back to...
While learning SpinalHDL，when using bus slave Factory，I have some questions： In bus slave Factory ，the follow scala code： `val axiLite4Ctrl=new Area { val axiLite4Ctrl=new AxiLite4SlaveFactory(io.axiLite4) axiLite4Ctrl.readAndWrite(pwmGen.enable,0,0,"Pwm Enable bit") axiLite4Ctrl.readAndWrite(pwmGen.dutyCycle,4,documentation ="duty...
