SpinalHDL
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SpinalHDL
Scala based HDL
After using spinalHDL for a while, No wonder this is a good alternative to HDL language. But I think there are still some things for improvement 1、The top thing annoying...
I'm almost finish my design, and about to do synthesize. But my mentor ask me to pull all the ram ports to the top level IO If it's a normal...
We want to know that whether SpinalHDL supports for loop support for verilog or not! Thanks
May I present you a foot gun: ``` val tuple = TupleBundle2(U(4, 32 bits), True) ``` Contrary to what one would expect, this code does **not** initialize `tuple` with `4`...
I don't know how, but I happened to produce a `switch` statement with the following syntax: ```scala switch(number) { 0 -> {}, 1 -> {}, 2 -> {}, } ```...
So it's really not a problem of SpinalHDL, but I think you can give me some help! I try to run spinal with Scastie, (https://scastie.scala-lang.org) I set "fork := true"...
In Apb3CCToggle, I think only the "hit" and "target" are needed to be synchronized by BufferCC. All other signals, such as PADDR, PSEL, PWRITE, PWDATA, PRDATA and so on are...
I can create a component with the name `Accumulator (128 bits)`. However, this will be used directly in Verilog without escaping, and thus produce syntax errors. Either restrict `setDefinitionName` to...
When I was writing test code, I found an interesting question. // todo vtype_t is a bundle val rst = ClockDomain.current.reset.pull() val tmp = (vtype_t().getZero).setAsReg().allowOverride // todo It's work, tmp...
Hello ! When I was rewriting the SV code, I found some unexplainable phenomena. The correct and runnable code is on the next line of todo. And the variable result_d...