SpinalHDL

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How to deal with "Error: Could not find or load main class projectname.MyTopLevelVerilog" for the SpinalTemplateSbt.git?

2

I'm a new user of SpinalHDL. I installed all the requirements and then git clone SpinalTemplateSbt.git. When I was excited to use IntelliJ to generate the first Verilog file, I...

xcfuisnewhere

Wrong address mapping in RamInst when using AxiLite4Businterface

1

The logic for the address of the `MemBus` of the `RamInst `object returned by the `newRAM` method of `AxiLite4BusInterface` is: ` bus.addr := (bi.readAddress - U(addr)).dropLow(bi.underbitWidth).asUInt.resized` This causes the AxiLite4...

XDH-233

Simulation Kernel Library Not Found (`librdi_simulator_kernel.dll`)

3

#### Description: Simulation fails to load the required shared library `librdi_simulator_kernel.dll`. This may be due to [the recent renaming of the kernel library in Vivado 2024.2](https://adaptivesupport.amd.com/s/article/000037038). #### System Information: -...

skylayer

could you support some descriptions about case class SpinalConfig parameter in spinal document?

2

the case class SpinalConfig for the generation of the RTL, has many parameters. it's difficult for users like me to know the meaning and usage of them. It's important for...

littlezpf666

[Axi4Master] Here's a bug in spinal/lib/bus/amba4/axi/sim/Axi4Master.writeSingle

7

val strb = if (len == 0) { ((BigInt(1)

Mxy97

Byte Mask Write for URAM Synthesized as Multiple BRAMs Instead of Single URAM

8

Hi @Dolu1990, I am testing the byte mask write functionality for URAM (UltraRAM) in SpinalHDL. I expect the generated Verilog to infer a single URAM with byte write enables. However,...

szNightFury

`Interface`-related SystemVerilog Code Emission Enhancements

4

Here's a link to the issue: https://github.com/SpinalHDL/SpinalHDL/issues/1633 # Context, Motivation & Description SystemVerilog `interface`s do not strictly have to have `modport`s. They can be much like a SpinalHDL `Bundle`s (without...

fl4shk

Pull request: https://github.com/SpinalHDL/SpinalHDL/pull/1631 I put a description of the changes I developed in the pull request. I noticed that I screwed up and didn't create an issue for the pull...

fl4shk

improve signal width inferrence

13

Hi, for below demo, spinal throw width mismatch error. ```scala case class Demo() extends Component { val io = new Bundle { val din = in UInt (4 bits) val...

facebreeze

Fix simulation failure with Verilator v5.x on Windows

7

Closes #1572 # Context, Motivation & Description Simulation with verilator v5.x on Windows will fail with the following error: ```powershell Program 'verilator_bin.exe' failed to run: The specified executable is not...

du33169