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Scala based HDL

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Hi, talking about latches (let's say today is Latch day ;) ), even if they are rarely used, they might be useful (for instance in describing clock gating cells). I...

enhancement

generate blackbox as below ``` def main(args: Array[String]): Unit = { val gw1n = GenBlackbox( ivlPathStr = "C:\\iverilog\\bin\\iverilog.exe", srcFileStr = "E:\\working\\working\\SpinalAll\\SpinalHDL\\lib\\src\\main\\scala\\spinal\\lib\\blackbox\\gowin\\gw1n\\prim_syn.v" ) val gw1ns = GenBlackbox( ivlPathStr = "C:\\iverilog\\bin\\iverilog.exe", srcFileStr...

There is the expression `HSEL && HREADY && HTRANS(1)` in [AhbLite3.scala:143](https://github.com/SpinalHDL/SpinalHDL/blob/dev/lib/src/main/scala/spinal/lib/bus/amba3/ahblite/AhbLite3.scala#L143). This expression is also used - in [AhbLite3OnChipRam.scala:70](https://github.com/SpinalHDL/SpinalHDL/blob/dev/lib/src/main/scala/spinal/lib/bus/amba3/ahblite/AhbLite3OnChipRam.scala#L70), - in [AhbLite3OnChipRom.scala:52](https://github.com/SpinalHDL/SpinalHDL/blob/dev/lib/src/main/scala/spinal/lib/bus/amba3/ahblite/AhbLite3OnChipRom.scala#L52), - and in [AhbLite3ToApb3Bridge.scala:69](https://github.com/SpinalHDL/SpinalHDL/blob/dev/lib/src/main/scala/spinal/lib/bus/amba3/ahblite/AhbLite3ToApb3Bridge.scala#L69). It is also in...

feature :sparkles:
good first issue

Because of #607, I thought about exchanging Verilator for IVerilog and see if it helps. Adding `simConfig.withIVerilog` and then running it again gave me the following: ```scala [Progress] IVerilog compilation...

Hello, A feature idea for a far future: Designers can use [Wavedrom](https://github.com/wavedrom/wavedrom) to [easily build waveforms](https://wavedrom.com/editor.html) with inputs and outputs of the component. The generated waveform can then be added...

Its OK in windows or use 1.6.4 in Linux, include centos 7.9 and ubuntu 18.04

When i use spinalsim to simulate my code, i write some code as below: `forkSensitive2(io.bus.rd_req, io.bus.rd_ptr) { io.bus.rd_stm #= Random.nextInt() & 0xff } ` io.bus.rd_req, io.bus.rd_ptr are outputs of dut....

Hello, Does SpinalHDL support test coverage? In the repository I've found the commit https://github.com/SpinalHDL/SpinalHDL/commit/33d9bcbeca3e6aed09a6483e201d06cc6b17551f which seems to add the feature but I couldn't find the documentation for it. I tried...

Contributor Checklist - [x] Did you add some test code? - [x] Did you add appropriate documentation in docs/src? - [x] Did you state the API impact? - [ ]...