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Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

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Chisel: A Modern Hardware Design Language

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VeeR EH1 core

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Rocket Chip Generator

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Test suite designed to check compliance with the SystemVerilog standard.

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SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

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VeeR EL2 Core

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Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in...

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Flexible Intermediate Representation for RTL

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