systemverilog topic

SystemVerilog to Verilog conversion

zachjs

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

trivialmips

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in...

chipsalliance

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

WangXuan95

SystemVerilog compiler and language services

MikePopoloski

80186 compatible SystemVerilog CPU core and FPGA reference design

jamieiles

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

TerosTechnology

SystemVerilog language server

dalance

Functional verification project for the CORE-V family of RISC-V cores.

openhwgroup

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

veripool