Rupert Swarbrick

## Commits since Earlgrey-ES tapeout As of commit: 2714197f32 ``` $ git log Earlgrey-M2.5.2-RC0..HEAD --oneline hw/ip/pattgen ``` gives: - 61a237e197 [util/reggen] reverse order of substruct generation - de31bdf1c2 [reggen] Remove...

D2S issue now closed (it was easier than this one!). Closing this as discussed above.

Please could you chop this up into one commit per sequence, and one PR per commit? It should make the review much simpler.

Thanks for chopping things up. I think I've still got one question about the testplan update (https://github.com/lowRISC/opentitan/pull/21381#discussion_r1490918576), but otherwise I think it looks sensible.

I've merged the change to the testplan (thanks). I think the head of this branch no longer contains an actual test implementation. Did you intend that to be here?

Hmm, this might be a problem with Questa support. At lowRISC, we don't currently have Questa access so it's rather hard for us to help. Can you reproduce the problem...

The code you've pinpointed is part of `riscv-dv`: a random instruction generator that we use as a dependency. Looking at it briefly, this seems to tell the generated binary to...

The error that you've sent a screenshot about is not connected to your choice of simulator. The problem here is that pkgconfig doesn't know that `riscv-riscv`, `riscv-disasm` and `riscv-fdt` are...

Hmm, that's not a great error message on our end (sorry). I've just looked at the Python and it's complaining that `rtl_log` didn't get substituted in the command (see the...

@hcallahan-lowrisc: I think this code came from you in the first place. Would you mind taking a look and trying to work out what has come unstuck?